An ever present goal in the semiconductor industry has been to decrease the size of devices, and to increase the performance of devices. However, both of these goals present large technical hurdles as the two goals are often in conflict with each other.
As the minimum feature size achievable in semiconductor manufacturing decreases, the capacitive coupling between adjacent metal lines becomes a significant impediment to achieving higher performance. Further, as the minimum feature size decreases the number of devices potentially achievable in a given area increases, as a second power function. The number of wiring connections is increasing at least as rapidly. In order to accommodate the increased wiring, the chip designer would like to shrink the space between adjacent lines to the minimum achievable dimension. This has the unfortunate effect of increasing the capacitive load.
One way to accommodate the increased wiring and reduce capacitive load is to substitute lower dielectric constant materials for the insulating material. A common insulating material to date is SiO2, which has a dielectric constant of around 4, is now used in most very large scale integrated circuit (VLSI) chips. Another way to accommodate the increased wiring and reduce capacitive load is to shorten the distance between devices by more dense packaging.
What is needed is a device design and method that improves the performance and reduces the size of a multi-chip assembly. Specifically, devices and methods are needed that utilize improved insulating materials. Further, devices and methods are needed that utilize improved dense packaging configurations.